VHDL-Forum

diego · Gast

hello,
I have a problem whit this code of counter

-- RR Generator
-- Specific Counter Module
-- Module of Counter : 8
-- VHDL Description code

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity countermod8 is
port(
ENABLE : in std_logic;
CLK : in std_logic;
RESET : in std_logic;
Y : out std_logic_vector(3 downto 0)
);
end countermod8;

architecture counter of countermod8 is
signal Z : std_logic_vector (3 downto 0);

begin
count_proc: process( clk, reset )
begin
if reset = '1' then
if ( enable = '1' ) then
Z <= ( others => '0' );
end if;
else
if clk'event and clk = '1' then
if ( enable = '1' ) then
if Z = "0111" then
Z <= ( others => '0' );
else
Z <= Z + 1;
end if;
else
Z <= Z;
end if;
end if;
end if;
end process;

end counter;

The error is at line " Z <= Z + 1; "
and wen i simulate whit modelsim thisi is a error:

No feasible entries for infix operator "+".
Type error resolving infix expression "+".

why???

thanks a lot Diego

PletzerC · Neuling Beiträge: 5

Zitat:

hello,
I have a problem whit this code of counter

-- RR Generator
-- Specific Counter Module
-- Module of Counter : 8
-- VHDL Description code

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity countermod8 is
port(
ENABLE : in std_logic;
CLK : in std_logic;
RESET : in std_logic;
Y : out std_logic_vector(3 downto 0)
);
end countermod8;

architecture counter of countermod8 is
signal Z : std_logic_vector (3 downto 0);

begin
count_proc: process( clk, reset )
begin
if reset = '1' then
if ( enable = '1' ) then
Z <= ( others => '0' );
end if;
else
if clk'event and clk = '1' then
if ( enable = '1' ) then
if Z = "0111" then
Z <= ( others => '0' );
else
Z <= Z + 1;
end if;
else
Z <= Z;
end if;
end if;
end if;
end process;

end counter;

The error is at line " Z <= Z + 1; "
and wen i simulate whit modelsim thisi is a error:

No feasible entries for infix operator "+".
Type error resolving infix expression "+".

why???

thanks a lot Diego

Hallo Diego

do nor use "signal Z" as logic vector-> use it as unsigned

signal Z : unsigned (3 downto 0);

if you are using it that way you have to change

if Z = "0111" then

to

if Z = 7 then

whar should the

else
Z <= Z;

be fore?

I'm very sorry for my bad english but i hob i coult help you

Chris

Lanze · Gast

Hi,

in my opinion the error in the colum is the absence of the Ticks:

Z <= Z + '1';

cause you initialize Z as std_logic_vector.

xGCFx · Stammgast Beiträge: 33 Ort: Dresden

Right,
you must use is as follows:

Z <= Z + 1;

and include the ieee.std_logic_unsigned lib.

Gast · Erstellt: 15.04.08, 13:53 Betreff: Re: problem counter vhdl

Zitat: diego

hello,
I have a problem whit this code of counter

-- RR Generator
-- Specific Counter Module
-- Module of Counter : 8
-- VHDL Description code

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity countermod8 is
port(
ENABLE : in std_logic;
CLK : in std_logic;
RESET : in std_logic;
Y : out std_logic_vector(3 downto 0)
);
end countermod8;

architecture counter of countermod8 is
signal Z : std_logic_vector (3 downto 0);

begin
count_proc: process( clk, reset )
begin
if reset = '1' then
if ( enable = '1' ) then
Z <= ( others => '0' );
end if;
else
if clk'event and clk = '1' then
if ( enable = '1' ) then
if Z = "0111" then
Z <= ( others => '0' );
else
Z <= Z + 1;
end if;
else
Z <= Z;
end if;
end if;
end if;
end process;

end counter;

The error is at line " Z <= Z + 1; "
and wen i simulate whit modelsim thisi is a error:

No feasible entries for infix operator "+".
Type error resolving infix expression "+".

why???

thanks a lot Diego