VHDL-Forum

Jean · Gast

Hi,

I'm doing a VHDL entity which has one generic of type std_logic_vector, somethin like this:

entity Encoder is
generic(POLY: std_logic_vector := "11101010");
port(CLK, RST, EN_c, c_in : in std_logic;
c_out : out std_logic);
end Encoder;

The problem now is that the direction of POLY is not defined, or is it? It seems that Modelsim interprets the direction as upwards by default i.e. POLY(0) refers to the left-most bit '1', not to the right-most bit '0'. But will all simulators and synthesis tools interpret it similarly?

Can I somehow force the direction of POLY into downward direction (downto) without telling the exact length of the vector e.g. without writing: POLY: std_logic_vector (7 downto 0) := "11101010"); ?? The length of POLY will vary, so I want to avoid writing the exact length e.g. 7 downto 0 every time the POLY changes.

Thanks and sorry for the english, my german isn't too goot yet!

Jean