VHDL-Forum

Yves · Gast

hi!
I'm french (that why i'm writing in english) and I've a problem. I'm trying to connect to component which common signals are "signed" type.

Here is my code :

library IEEE;
use IEEE.STD_LOGIC_1164.all;
--use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;

------------------------------------------------------------------
--
--
-- you put an angle (integer) and the result is the sinus and
-- cosinus of this angle
--
------------------------------------------------------------------

entity Driver_Sram_Vga_conv_cordic is
Port (
clk : in std_logic; -- clk card

A_integer : in integer range 0 to 65535 ;

cos_integer : out integer range 0 to 65535 ;
sin_integer : out integer range 0 to 65535 );

end Driver_Sram_Vga_conv_cordic;

architecture TransmicionandRecepcion of Driver_Sram_Vga_conv_cordic is

-------------------------------------------------------------------
--
-- first component
--
-------------------------------------------------------------------

component Conv_integer_signed
port(
clk : in std_logic;

A_integer : in integer range 0 to 65535 ;
A_signed : out signed (15 downto 0);

cos_signed : in signed (15 downto 0) ;
cos_integer : out integer range 0 to 65535 ;

sin_signed : in signed (15 downto 0) ;
sin_integer : out integer range 0 to 65535 );
end component;

-------------------------------------------------------------------
--
-- second component
--
-------------------------------------------------------------------

component sc_corproc
port(
clk : in std_logic;

Ain : in signed(15 downto 0);

sin : out signed(15 downto 0);
cos : out signed(15 downto 0));
end component;

-------------------------------------------------------------------
--
-- declaration of the signals to link the 2 blocs
--
-------------------------------------------------------------------

signal cos_signed : SIGNED(15 downto 0);
signal sin_signed : SIGNED(15 downto 0);
-- Observed signals - signals mapped to the output ports of tested entity
signal A_signed : SIGNED(15 downto 0);

begin

-------------------------------------------------------------------
--
-- declaration of the link between the 2 blocs
--
-------------------------------------------------------------------

adaptation : Conv_integer_signed
port map(
clk => clk,

A_integer => A_integer,
A_signed => A_signed,

cos_signed => cos_signed,
cos_integer => cos_integer,

sin_signed => sin_signed,
sin_integer => sin_integer );

Cordic : sc_corproc
port map(
clk => clk,
Ain => A_signed,

sin => sin_signed,
cos => cos_signed );

end TransmicionandRecepcion;

Here is the error message with active HDL :

# Error: ELAB1_0021: Driver_Sram_Vga_conv.vhd : (88, 0): Types do not match for port "A_signed".
# Error: ELAB1_0021: Driver_Sram_Vga_conv.vhd : (88, 0): Types do not match for port "cos_signed".
# Error: ELAB1_0021: Driver_Sram_Vga_conv.vhd : (88, 0): Types do not match for port "sin_signed".

Here is the error message withLeonardoSpectrum :

line 99: Error, cannot associate type SIGNED for A_signed with type SIGNED for A_signed.
line 99: Error, cannot associate type SIGNED for cos_signed with type SIGNED for cos_signed.
line 99: Error, cannot associate type SIGNED for sin_signed with type SIGNED for sin_signed.

I really don't understand, that doesn't work, if anybody knows why...
Thanks a lot,
Yves