VHDL-Forum

ontos · Neuling Beiträge: 5

Warum gibt es solche fehler, wenn ich Component benutze?
Dieser Satz macht alles schlecht
komp1: n2 PORT MAP(s,r,q);

Error (10565): VHDL Binding Indication error at entity2_1.vhd(19): design entity "entity2" does not contain port "a" specified in associated component
Info (10499): VHDL information: object "entity2" is declared at entity2_1.vhd(5)
Error (10346): VHDL error at entity2_1.vhd(6): formal port or parameter "s" must have actual or default value
Error (10346): VHDL error at entity2_1.vhd(6): formal port or parameter "r" must have actual or default value

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY entity2 IS
PORT(s,r: IN STD_LOGIC;
q: OUT STD_LOGIC);
END entity2;

ARCHITECTURE nand2_struct OF entity2 IS
BEGIN
q<=s NAND r;
END nand2_struct;

ARCHITECTURE Struktura OF entity2 IS
COMPONENT n2 PORT(a,b: IN STD_LOGIC; y: OUT STD_LOGIC);
END COMPONENT;
FOR ALL:n2 USE ENTITY WORK.entity2(nand2_struct);
BEGIN
komp1: n2 PORT MAP(s,r,q);
END Struktura;