VHDL-Forum

ontos · Neuling Beiträge: 5

Ich schreibe alles Program, um leichter das Problem zu losen.

LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY light IS
PORT ( x1, x2, Clk : IN STD_LOGIC ;
f,f2,LCD_ON, LCD_BL : OUT STD_LOGIC ) ;
END light ;
ARCHITECTURE LogicFunction OF light IS
BEGIN
f <= (x1 AND NOT x2) OR (NOT x1 AND x2) AFTER 200 NS;
f2 <= (x1 AND NOT x2) OR (NOT x1 AND x2) AFTER 500 NS;
LCD_ON <= '1' AFTER 200 NS;
LCD_BL <= '1';
END LogicFunction ;

So sieht Waveform aus: